1. Field
This disclosure relates to circuits to provide other components with protection against overvoltage, such as electrostatic discharge (ESD) and/or electrical overstress (EOS) events.
2. Description of the Related Technology
Modern electronics relies on integrated circuits where large numbers of transistors are provided within a single package. For performance, such as speed, the transistors are often designed to operate at relatively low voltages, for example, between a few volts and a few tens of volts.
Integrated circuits are packaged to protect them, but need to connect to components outside of the package by way of legs or pins or similar structures. These may in turn connect to terminals, connectors or sockets provided on a product in which the integrated circuit is provided. Thus, even when an integrated circuit is mounted on a circuit board, it can be subjected to electrostatic shocks. It is known that integrated circuits waiting to be placed on a circuit board are especially vulnerable to electrostatic discharge or other overvoltage events.
It is desirable, and known, to provide circuits that provide overvoltage protection. Simple examples are the provision of reverse biased diodes between a node to be protected and the supply rails of an integrated circuit.
However, in more sophisticated voltage protection circuits it is desirable that:                1) The circuit does not trigger until a trigger voltage is reached.        2) That once the circuit has triggered, the voltage “snaps back” to a smaller holding voltage.        3) The circuit is fast so that it can respond to an ESD event before damage occurs to the integrated circuit.        
Performance of the circuits can be assessed against several published test standards. One such standard is the International Electrotechnical Commission (IEC) CDM (charged device model) where peak current can be in the range of 6 A with a rise time of less than 400 pico-seconds. ESD events of this nature may give rise to gate oxide damage of MOSFETs, junction damage and charge trapping with integrated circuits.
It is desirable to provide a robust and a fast protection circuit.